پاورپوینت کامل VHDL Synthesis Techniques and Recommendations 27 اسلاید در PowerPoint

قسمتی از پاورپوینت :

Synthesis is the translation process from an abstract description of a hardware device into an optimized technology specific gate level implementation
May be done
Manually via schematic entry
Automatically via EDA tools that use a hardware description language (HDL) as an input medium to generate constraint driven gate configurations.
Pre-Synthesis Steps
Functional Specification of the design
Design Entry
HDL Coding in VHDL/Verilog RTL
Graphical Entry Tools
Summit Design (Visual XOR)
SpeedChart (Speed Electronics)
Simulation Graphical Environment (Synopsys SGE)
Design Source (Synopsys)
Design Manager (Mentor)
View Draw (Viewlogic)
Escalade (Design Book)
Pre-Synthesis Steps
RTL/Behavioral or Functional Simulation of the HDL
Model Technologies (MTI)
Quicksim (Mentor)
Synopsys VHDL System Simulator (VSS)
Vantage (ViewLogic)
Leapfrog (Cadence)
Verilog XL(Cadence)
Chronologic (Viewlogic)
SYNTHESIS: Logic synthesis is the process of translating and optimizing a high-level design description to gates from a technolgy library